Paper Details

Name: Pooja Kumari
Country: India

Year: 2025
Volume: Volume-12, Issue-1 (January-June)
Page Number: 81-190
DOI: https://doi.org/10.5281/zenodo.17813613

ABSTRACT
Conventional MOSFET scaling has been driven for decades by classical electrostatic
considerations and Dennard scaling rules. As the physical gate length approaches and falls
below 5 nm, however, quantum-mechanical phenomena, especially source–drain tunnelling,
quantum confinement, gate-oxide tunnelling and ballistic transport, become the dominant
factors limiting further scaling. This paper presents a theoretical, quantum-mechanical limit
analysis of MOSFET scaling in the sub-5 nm regime, using scale-length theory, Landauer–
Datta transport, and benchmark data from state-of-the-art silicon and two-dimensional (2D)
material devices. We review classical scaling and its breakdown, quantify tunnelling-driven
leakage and subthreshold swing limits, and discuss ballistic current saturation for
aggressively scaled channels. Using published ab initio quantum-transport simulations of
sub-5 nm monolayer and bilayer MOSFETs (e.g., MoSi₂N₄, GaSe, SnS₂), we construct
illustrative plots of on-current, subthreshold swing, and Ion/Ioff versus gate length and
compare them with IRDS/ITRS targets for high-performance and low-power logic. Our
analysis suggests that for silicon-based MOSFETs operating at room temperature and
realistic supply voltages, practical logic devices face severe trade-offs below an effective gate
length of ~5–7 nm because of exponentially rising tunnelling leakage and loss of electrostatic
control, even with multi-gate architectures. In contrast, 2D semiconductors with large
bandgaps and high effective mass can in principle sustain competitive Ion at gate lengths
down to ~2–3 nm, but only with optimised gate stacks, dielectric engineering, and nearly
ballistic transport. The paper concludes with design guidelines and a discussion of whether
further ―Moore-like‖ scaling should focus on III–V and 2D channels, new switching
mechanisms, or system-level architectural innovations, rather than purely geometric
shrinking of Si MOSFETs.
Keywords: MOSFET scaling, sub-5 nm gate length, quantum transport, source–drain
tunnelling, ballistic MOSFET, 2D materials, Landauer formalism, IRDS.